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SBAU337–May 2020
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Serial Interface Register Maps
2.14.118 Register 462h (offset = 462h) [reset = 0h]
Figure 2-2001. Register 462h
7 6 5 4 3 2 1 0
FB_AGC_LNA_RF_DET_ATTACK_NUM_HITS[23:16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2015. Register 462 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_LNA_RF
_DET_ATTACK_N
UM_HITS[23:16]
R/W 0h
LNA RF attack det threshold. If Number of hits is greater than
this, detector is triggered. Note that per clock we may get up
to 8 hits.
2.14.119 Register 463h (offset = 463h) [reset = 8h]
Figure 2-2002. Register 463h
7 6 5 4 3 2 1 0
FB_AGC_LNA_RF_DET_ATTACK_NUM_HITS[27:24]
R/W-8h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2016. Register 463 Field Descriptions
Bit Field Type Reset Description
3-0
FB_AGC_LNA_RF
_DET_ATTACK_N
UM_HITS[27:24]
R/W 8h
LNA RF attack det threshold. If Number of hits is greater than
this, detector is triggered. Note that per clock we may get up
to 8 hits.
2.14.120 Register 498h (offset = 498h) [reset = 2h]
Figure 2-2003. Register 498h
7 6 5 4 3 2 1 0
FB_AGC_EXT_
MODE
FB_AGC_INTE
RNAL_EN
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2017. Register 498 Field Descriptions
Bit Field Type Reset Description
1-1
FB_AGC_EXT_MO
DE
R/W 1h
Bit indicating system is in External AGC mode. In this mode
seperate configurability exists on when and whether to reset
the peak detectors when external DSA Gain has changed.
0 : Internal AGC Mode
1 : External AGC Mode
0-0
FB_AGC_INTERN
AL_EN
R/W 0h
Internal AGC control loop enable
0 : Use Default attn
1 : Internal AGC enabled