IO Wrap Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.16.535 Register A0Ch (offset = A0Ch) [reset = 0h]
Figure 2-2798. Register A0Ch
7 6 5 4 3 2 1 0
SEL_INTPI_TX_GAIN_SW_0 POL_INTPI_TX
_GAIN_SW_0
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2814. Register A0C Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TX_G
AIN_SW_0
R/W 0h
select control for intpi_tx_gain_sw_0. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TX_G
AIN_SW_0
R/W 0h
polarity control for intpi_tx_gain_sw_0. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.536 Register A0Dh (offset = A0Dh) [reset = 2h]
Figure 2-2799. Register A0Dh
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TX_GAIN_S
W_0
OVR_INTPI_TX
_GAIN_SW_0
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2815. Register A0D Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TX_GAIN_SW_0
R/W 1h
control to select whether the input function intpi_tx_gain_sw_0
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TX_G
AIN_SW_0
R/W 0h override value for ovr_sel_intpi_tx_gain_sw_0 is made high
2.16.537 Register A10h (offset = A10h) [reset = 0h]
Figure 2-2800. Register A10h
7 6 5 4 3 2 1 0
SEL_INTPI_TX_GAIN_SW_1 POL_INTPI_TX
_GAIN_SW_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2816. Register A10 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TX_G
AIN_SW_1
R/W 0h
select control for intpi_tx_gain_sw_1. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TX_G
AIN_SW_1
R/W 0h
polarity control for intpi_tx_gain_sw_1. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
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