Texas Instruments AFE79 Series - 2.5.208 Register 124 h (offset = 124 h) [reset = 0 h]; 2.5.209 Register 125 h (offset = 125 h) [reset = 0 h]

ADC JESD Register Map www.ti.com
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SBAU337–May 2020
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Serial Interface Register Maps
2.5.208 Register 124h (offset = 124h) [reset = 0h]
Figure 2-704. Register 124h
7 6 5 4 3 2 1 0
CLEAR_JESD_
CLK_FB_P0
CLEAR_JESD_
CLK_RX2_P2
CLEAR_JESD_
CLK_RX2_P0
CLEAR_JESD_
CLK_RX1_P2
CLEAR_JESD_
CLK_RX1_P0
CLEAR_DDC_
RD_CLK_FB
CLEAR_DDC_
RD_CLK_RX2
CLEAR_DDC_
RD_CLK_RX1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-709. Register 124 Field Descriptions
Bit Field Type Reset Description
7-7
CLEAR_JESD_CL
K_FB_P0
R/W 0h
when set to 1, clears the MONITOR_JESD_CLK_FB_P0
register
6-6
CLEAR_JESD_CL
K_RX2_P2
R/W 0h
when set to 1, clears the MONITOR_JESD_CLK_RX2_P2
register
5-5
CLEAR_JESD_CL
K_RX2_P0
R/W 0h
when set to 1, clears the MONITOR_JESD_CLK_RX2_P0
register
4-4
CLEAR_JESD_CL
K_RX1_P2
R/W 0h
when set to 1, clears the MONITOR_JESD_CLK_RX1_P2
register
3-3
CLEAR_JESD_CL
K_RX1_P0
R/W 0h
when set to 1, clears the MONITOR_JESD_CLK_RX1_P0
register
2-2
CLEAR_DDC_RD_
CLK_FB
R/W 0h
when set to 1, clears the MONITOR_DDC_RD_CLK_FB
register
1-1
CLEAR_DDC_RD_
CLK_RX2
R/W 0h
when set to 1, clears the MONITOR_DDC_RD_CLK_RX2
register
0-0
CLEAR_DDC_RD_
CLK_RX1
R/W 0h
when set to 1, clears the MONITOR_DDC_RD_CLK_RX1
register
2.5.209 Register 125h (offset = 125h) [reset = 0h]
Figure 2-705. Register 125h
7 6 5 4 3 2 1 0
CLEAR_JESD_
CLK_RX2_P0_
MSF_RD
CLEAR_JESD_
CLK_RX1_P0_
MSF_RD
CLEAR_JESD_
CLK_DIV2_FB_
P3
CLEAR_JESD_
CLK_DIV2_FB_
P1
CLEAR_JESD_
CLK_DIV2_RX
2_P2
CLEAR_JESD_
CLK_DIV2_RX
1_P0
CLEAR_JESD_
CLK_FB_P3
CLEAR_JESD_
CLK_FB_P1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-710. Register 125 Field Descriptions
Bit Field Type Reset Description
7-7
CLEAR_JESD_CL
K_RX2_P0_MSF_
RD
R/W 0h UNUSED
6-6
CLEAR_JESD_CL
K_RX1_P0_MSF_
RD
R/W 0h UNUSED
5-5
CLEAR_JESD_CL
K_DIV2_FB_P3
R/W 0h
when set to 1, clears the
MONITOR_JESD_CLK_DIV2_FB_P3 register
4-4
CLEAR_JESD_CL
K_DIV2_FB_P1
R/W 0h
when set to 1, clears the
MONITOR_JESD_CLK_DIV2_FB_P1 register
3-3
CLEAR_JESD_CL
K_DIV2_RX2_P2
R/W 0h
when set to 1, clears the
MONITOR_JESD_CLK_DIV2_RX2_P2 register
2-2
CLEAR_JESD_CL
K_DIV2_RX1_P0
R/W 0h
when set to 1, clears the
MONITOR_JESD_CLK_DIV2_RX1_P0 register