Texas Instruments AFE79 Series - 2.6.124 Register 49 DFh (offset = 49 DFh) [reset = 0 h]; 2.6.125 Register 49 E0 h (offset = 49 E0 h) [reset = 0 h]; 2.6.126 Register 49 E1 h (offset = 49 E1 h) [reset = 0 h]

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Serial Interface Register Maps
2.6.124 Register 49DFh (offset = 49DFh) [reset = 0h]
Figure 2-838. Register 49DFh
7 6 5 4 3 2 1 0
INTP_INIT_EN INTP_INIT_VAL
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-844. Register 49DF Field Descriptions
Bit Field Type Reset Description
7-7 INTP_INIT_EN R/W 0h
When enabled, INTP_INIT_VAL is used.
0: Disable
1: Enable
6-0 INTP_INIT_VAL R/W 0h PLL interpolator value.
2.6.125 Register 49E0h (offset = 49E0h) [reset = 0h]
Figure 2-839. Register 49E0h
7 6 5 4 3 2 1 0
OW_FREQ_ACC_TOP[6:0] RECOVERED_
CLK_SEL
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-845. Register 49E0 Field Descriptions
Bit Field Type Reset Description
7-1
OW_FREQ_ACC_
TOP[6:0]
R/W 0h
0-0
RECOVERED_CL
K_SEL
R/W 0h
Mux control bit selecting lane RX recovered clock or external
recovered clock as input for TX PLL.
0h: External recovered clock.
1h: master rx_sel clk. When this is selected, bit 15:14 are
used.
2.6.126 Register 49E1h (offset = 49E1h) [reset = 0h]
Figure 2-840. Register 49E1h
7 6 5 4 3 2 1 0
LANE_RCVD_CLK_SRC OWEN_FREQ_
ACC_TOP
OW_FREQ_ACC_TOP[11:7]
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-846. Register 49E1 Field Descriptions
Bit Field Type Reset Description
7-6
LANE_RCVD_CLK
_SRC
R/W 0h
Mux control bit selecting lane RX recovered clock for TX PLL.
0h: Lane 0
1h: Lane 1
2h: Lane 2
3h: Lane 3
5-5
OWEN_FREQ_AC
C_TOP
R/W 0h