Texas Instruments AFE79 Series - 2.3.86 Register 9 Eh (offset = 9 Eh) [reset = 3 h]

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SBAU337–May 2020
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Table 2-129. Register 9D Field Descriptions
Bit Field Type Reset Description
6-6
RX_CLK_DIV4_CO
MMON_PHASE_DI
SABLE
R/W 0h
setting this to '1' will disable all clk-phases
0 : Enable
1 : Disable
5-5
RX_CLK_DIV4_PH
ASE4_DISABLE
R/W 1h
setting this to '1' will disable clock div8_phase4
0 : Enable
1 : Disable
4-4
RX_CLK_DIV4_PH
ASE3_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase3
0 : Enable
1 : Disable
3-3
RX_CLK_DIV4_PH
ASE2_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase2
0 : Enable
1 : Disable
2-2
RX_CLK_DIV4_PH
ASE1_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase1
0 : Enable
1 : Disable
1-1
RX_CLK_DIV4_PH
ASE0_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase0
0 : Enable
1 : Disable
0-0
RX_CLK_DIV4_MU
LTIPHASE_DISAB
LE
R/W 0h
0 - div8 clocks will have 4 clock-phases
1 - div8 clocks will have a single-phase
0 : Enable multi-phase
1 : Disable multi-phase
2.3.86 Register 9Eh (offset = 9Eh) [reset = 3h]
Figure 2-127. Register 9Eh
7 6 5 4 3 2 1 0
FB_CLK_LFSR
_SEED_LOAD
FB_CLK_SYSR
EF_VAL
FB_CLK_SYSR
EF_SEL
FB_CLK_SYSREF_DELAY FB_CLK_DITH
ERED_MODE_
EN
FB_CLK_DISA
BLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-130. Register 9E Field Descriptions
Bit Field Type Reset Description
7-7
FB_CLK_LFSR_SE
ED_LOAD
R/W 0h
Loads the LFSR seed value when this is set to 1. Need to be
used along with 'tx_clk_lfsr_seed_val' register
0 : Use default LFSR seed value
1 : Load LFSR seed value from register
6-6
FB_CLK_SYSREF
_VAL
R/W 0h spi-based sysref
5-5
FB_CLK_SYSREF
_SEL
R/W 0h select spi-based sysref which is fb_clk_sysref_val
4-2
FB_CLK_SYSREF
_DELAY
R/W 0h delaying the sysref to the dithered clock generation
1-1
FB_CLK_DITHERE
D_MODE_EN
R/W 1h
set to 1 for dithering the clocks derieved from root-clk
0 : Disable clk dither
1 : Enable clk dither
0-0 FB_CLK_DISABLE R/W 1h
Disable clk-generation from this module
0 : Enable
1 : Disable