Texas Instruments AFE79 Series - 2.15.27 Register A1 h (offset = A1 h) [reset = 0 h]; 2.15.28 Register A2 h (offset = A2 h) [reset = 0 h]; 2.15.29 Register A3 h (offset = A3 h) [reset = 0 h]

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Serial Interface Register Maps
Table 2-2248. Register A0 Field Descriptions
Bit Field Type Reset Description
0-0
USE_PER_CH_RX
AB_TDD
R/W 0h
For rx tdd signals at ab side whether to enable per channel
control or not. By default per channel control is not enabled.
2.15.27 Register A1h (offset = A1h) [reset = 0h]
Figure 2-2234. Register A1h
7 6 5 4 3 2 1 0
USE_PER_CH
_RXCD_TDD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2249. Register A1 Field Descriptions
Bit Field Type Reset Description
0-0
USE_PER_CH_RX
CD_TDD
R/W 0h
For rx tdd signals at cd side whether to enable per channel
control or not. By default per channel control is not enabled.
2.15.28 Register A2h (offset = A2h) [reset = 0h]
Figure 2-2235. Register A2h
7 6 5 4 3 2 1 0
RXGSWAP_M
ODE_AB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2250. Register A2 Field Descriptions
Bit Field Type Reset Description
0-0
RXGSWAP_MODE
_AB
R/W 0h
In mode 0, both chA & chB get the same 2 bits for the gain
swap and in mode1, chA gets bit 0 of the input and chB gets
bit1of the input, in the LSB to each of the channels. MSB will
be zero.
2.15.29 Register A3h (offset = A3h) [reset = 0h]
Figure 2-2236. Register A3h
7 6 5 4 3 2 1 0
RXGSWAP_M
ODE_CD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2251. Register A3 Field Descriptions
Bit Field Type Reset Description
0-0
RXGSWAP_MODE
_CD
R/W 0h
In mode 0, both chC & chD get the same 2 bits for the gain
swap and in mode1, chC gets bit 0 of the input and chD gets
bit1of the input, in the LSB to each of the channels. MSB will
be zero.