IO Wrap Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.16.482 Register 8B1h (offset = 8B1h) [reset = 2h]
Figure 2-2745. Register 8B1h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_ADC_SYNC
_N_CD_1
OVR_INTPI_A
DC_SYNC_N_
CD_1
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2761. Register 8B1 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
ADC_SYNC_N_CD
_1
R/W 1h
control to select whether the input function
intpi_adc_sync_n_cd_1 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_ADC_
SYNC_N_CD_1
R/W 0h
override value for ovr_sel_intpi_adc_sync_n_cd_1 is made
high
2.16.483 Register 8B4h (offset = 8B4h) [reset = 0h]
Figure 2-2746. Register 8B4h
7 6 5 4 3 2 1 0
SEL_INTPI_ADC_SYNC_N_CD_
2
POL_INTPI_AD
C_SYNC_N_C
D_2
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2762. Register 8B4 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_ADC_
SYNC_N_CD_2
R/W 0h
select control for intpi_adc_sync_n_cd_2. 0 indicates take
from parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_ADC_
SYNC_N_CD_2
R/W 0h
polarity control for intpi_adc_sync_n_cd_2. 0 indicates pass
through from GPIO when selected 1 indicates inverted signal
2.16.484 Register 8B5h (offset = 8B5h) [reset = 2h]
Figure 2-2747. Register 8B5h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_ADC_SYNC
_N_CD_2
OVR_INTPI_A
DC_SYNC_N_
CD_2
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2763. Register 8B5 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
ADC_SYNC_N_CD
_2
R/W 1h
control to select whether the input function
intpi_adc_sync_n_cd_2 needs to be overriden ot not. 1
indicates override.
0-0
OVR_INTPI_ADC_
SYNC_N_CD_2
R/W 0h
override value for ovr_sel_intpi_adc_sync_n_cd_2 is made
high
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