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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1292. Register 391 Field Descriptions
Bit Field Type Reset Description
7-0
TX_DUC_MIXER2
_NCO0_PHASE_O
FFSET[15:8]
R/W 0h Offset phase for nco0 in Mixer 2
2.12.78 Register 392h (offset = 392h) [reset = 0h]
Figure 2-1281. Register 392h
7 6 5 4 3 2 1 0
TX_DUC_MIXER2_NCO1_PHASE_OFFSET[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1293. Register 392 Field Descriptions
Bit Field Type Reset Description
7-0
TX_DUC_MIXER2
_NCO1_PHASE_O
FFSET[7:0]
R/W 0h Offset phase for nco1 in Mixer 2
2.12.79 Register 393h (offset = 393h) [reset = 0h]
Figure 2-1282. Register 393h
7 6 5 4 3 2 1 0
TX_DUC_MIXER2_NCO1_PHASE_OFFSET[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1294. Register 393 Field Descriptions
Bit Field Type Reset Description
7-0
TX_DUC_MIXER2
_NCO1_PHASE_O
FFSET[15:8]
R/W 0h Offset phase for nco1 in Mixer 2
2.12.80 Register 3C0h (offset = 3C0h) [reset = 0h]
Figure 2-1283. Register 3C0h
7 6 5 4 3 2 1 0
TX_DUC_MIXER2_NCO0_FMULT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1295. Register 3C0 Field Descriptions
Bit Field Type Reset Description
7-0
TX_DUC_MIXER2
_NCO0_FMULT[7:
0]
R/W 0h
Frequency shift corresponding to the fcw of nco0 in Mixer2,
expressed in kHz, modulo Fdac/16. Value programmed here
should correspond to the nco0 fcw, and should be a value
between 0 and Fdac/16.
The System Configuration Macros automatically and optimally
partition the overall center frequency between Mixer1 and
Mixer2, and are hence strongly recommended.