JESD_SUBCHIP Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.3.47 Register 56h (offset = 56h) [reset = 53h]
Figure 2-88. Register 56h
7 6 5 4 3 2 1 0
ADC_JESD_SYNC_N5_MUX_SEL ADC_JESD_SYNC_N4_MUX_SEL
R/W-5h R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-91. Register 56 Field Descriptions
Bit Field Type Reset Description
6-4
ADC_JESD_SYNC
_N5_MUX_SEL
R/W 5h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for change the sync_n pin order.
Using LATTE to configure this register is recommended.
2-0
ADC_JESD_SYNC
_N4_MUX_SEL
R/W 3h
adc_jesd_sync_*_mux and adc_jesd_sync_*_reorder registers
together implement the sync reorder and broadcast
funcationlity.
This register is used for change the sync_n pin order.
Using LATTE to configure this register is recommended.
2.3.48 Register 57h (offset = 57h) [reset = 0h]
Figure 2-89. Register 57h
7 6 5 4 3 2 1 0
ADC_JESD_SY
NC_N5_INV
ADC_JESD_SY
NC_N4_INV
ADC_JESD_SY
NC_N3_INV
ADC_JESD_SY
NC_N2_INV
ADC_JESD_SY
NC_N1_INV
ADC_JESD_SY
NC_N0_INV
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-92. Register 57 Field Descriptions
Bit Field Type Reset Description
5-5
ADC_JESD_SYNC
_N5_INV
R/W 0h
To invert polarity of sync_n[5]
0 : No-invert
1 : Invert
4-4
ADC_JESD_SYNC
_N4_INV
R/W 0h
To invert polarity of sync_n[4]
0 : No-invert
1 : Invert
3-3
ADC_JESD_SYNC
_N3_INV
R/W 0h
To invert polarity of sync_n[3]
0 : No-invert
1 : Invert
2-2
ADC_JESD_SYNC
_N2_INV
R/W 0h
To invert polarity of sync_n[2]
0 : No-invert
1 : Invert
1-1
ADC_JESD_SYNC
_N1_INV
R/W 0h
To invert polarity of sync_n[1]
0 : No-invert
1 : Invert
0-0
ADC_JESD_SYNC
_N0_INV
R/W 0h
To invert polarity of sync_n[0]
0 : No-invert
1 : Invert
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