List of Macros
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SBAU337–May 2020
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Macro
Table 1-63.
Bit name Detector
Bit 14 Dig OVR Bit
Bit 13 RESERVED
Bit 12 Band 1 peak detector
Bit 11 LNARF detector
Bit 10 RESERVED
Bit 9 Band 2 peak detector
Bit 8 Reserved
Bit 7 Digital big step attack
Bit 6 Digital small step attack
Bit 5 Digital big step decay
Bit 4 Digital small step decay
Bit 3 Dig pwr attack
Bit 2 Dig pwr decay
Bit 1 RESERVED
Bit 0 RESERVED
The pulse expansion count indicates for how many cycles the trigger should be held.
1.2.5.6 AGC Detectors reset by GPIO Control Macro
Table 1-64.
Macro AGC Detectors reset by GPIO Control
Opcode 0x5D
Operand Offset Length Value Functionality Results
1 0x00 1 RX Channel Select Bit 0: 1 → Value
specified in
subsequent
operands is valid for
1RX.
Bit 1: 1 → Value
specified in
subsequent
operands is valid for
2RX.
Bit 2: 1 → Value
specified in
subsequent
operands is valid for
3RX.
Bit 3: 1 → Value
specified in
subsequent
operands is valid for
4RX.
Bit 4 → RESERVED
Bit 5 → RESERVED
2 0x01 1 GPIO based reset
to detectors Enable.
Memory Not used
Enables Control of peak detector reset using GPIO.This macro doesn’t perform any GPIO connections
(applicable only in External AGC mode).
See SBAA417 configuration document for configuration of GPIO.