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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-2122. Register 548 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BAND0_
LNA_PHASE6[7:0]
R/W 0h
LNA Phase for Band0 for temp index 6 in case of External
LNA Control , Phase for DVGA Index 6 in case of External
DVGA control
2.14.226 Register 549h (offset = 549h) [reset = 0h]
Figure 2-2109. Register 549h
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE6
[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2123. Register 549 Field Descriptions
Bit Field Type Reset Description
1-0
FB_AGC_BAND0_
LNA_PHASE6[9:8]
R/W 0h
LNA Phase for Band0 for temp index 6 in case of External
LNA Control , Phase for DVGA Index 6 in case of External
DVGA control
2.14.227 Register 54Ah (offset = 54Ah) [reset = 0h]
Figure 2-2110. Register 54Ah
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE7[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2124. Register 54A Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BAND0_
LNA_PHASE7[7:0]
R/W 0h
LNA Phase for Band0 for temp index 7 in case of External
LNA Control , Phase for DVGA Index 7 in case of External
DVGA control
2.14.228 Register 54Bh (offset = 54Bh) [reset = 0h]
Figure 2-2111. Register 54Bh
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE7
[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2125. Register 54B Field Descriptions
Bit Field Type Reset Description
1-0
FB_AGC_BAND0_
LNA_PHASE7[9:8]
R/W 0h
LNA Phase for Band0 for temp index 7 in case of External
LNA Control , Phase for DVGA Index 7 in case of External
DVGA control