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Texas Instruments AFE79 Series - 2.5.71 Register 78 h (offset = 78 h) [reset = 1 h]; 2.5.72 Register 79 h (offset = 79 h) [reset = 0 h]; 2.5.73 Register 7 Ah (offset = 7 Ah) [reset = 0 h]

Texas Instruments AFE79 Series
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ADC JESD Register Map
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410
SBAU337May 2020
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Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-571. Register 77 Field Descriptions
Bit Field Type Reset Description
7-7 LINK0_SCR R/W 0h
JESD link config for STX1/5
For JESD-B/C
When 1, scrambler (present between transport layer and link
layer) is enabled
1+x^14+x^15
0 : scrambler disabled
1 : scrambler enabled
6-5 0 R/W 0h Must read or write 0
4-0 LINK0_ILA_L_M1 R/W 1h
JESD link config for STX1/5
Used only when link0_jesd_ila_config_override is 1.
Else L derived from LMFS is used.
2.5.71 Register 78h (offset = 78h) [reset = 1h]
Figure 2-567. Register 78h
7 6 5 4 3 2 1 0
LINK0_ILA_F_M1
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-572. Register 78 Field Descriptions
Bit Field Type Reset Description
7-0 LINK0_ILA_F_M1 R/W 1h
JESD link config for STX1/5
Used only when link0_jesd_ila_config_override is 1.
Else F derived from LMFS is used.
2.5.72 Register 79h (offset = 79h) [reset = 0h]
Figure 2-568. Register 79h
7 6 5 4 3 2 1 0
LINK0_ILA_K_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-573. Register 79 Field Descriptions
Bit Field Type Reset Description
7-0 LINK0_ILA_K_M1 R/W 0h
JESD link config for STX1/5
Used only when link0_jesd_ila_config_override is 1.
Else picked from link0_k_m1.
2.5.73 Register 7Ah (offset = 7Ah) [reset = 0h]
Figure 2-569. Register 7Ah
7 6 5 4 3 2 1 0
LINK0_ILA_M_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

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