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ADC JESD Register Map
403
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-550. Register 5A Field Descriptions (continued)
Bit Field Type Reset Description
1-0
CTRL_JESD_CLK_
DIV2_RX2_P2
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
2.5.50 Register 5Ch (offset = 5Ch) [reset = 1Fh]
Figure 2-546. Register 5Ch
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_DI
V2_DITHER_E
N
JESD_CLK_DI
THER_EN
DDC_RD_CLK
_DITHER_EN
FB_ROOT_CL
K_DITHER_EN
RX_ROOT_CL
K_DITHER_EN
R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-551. Register 5C Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-4
JESD_CLK_DIV2_
DITHER_EN
R/W 1h
0 : dither disabled
1 : dither enabled
3-3
JESD_CLK_DITHE
R_EN
R/W 1h
0 : dither disabled
1 : dither enabled
2-2
DDC_RD_CLK_DI
THER_EN
R/W 1h
0 : dither disabled
1 : dither enabled
1-1
FB_ROOT_CLK_DI
THER_EN
R/W 1h
0 : dither disabled
1 : dither enabled
0-0
RX_ROOT_CLK_D
ITHER_EN
R/W 1h
1 : dither enabled
0 : dither disabled
2.5.51 Register 5Dh (offset = 5Dh) [reset = 1h]
Figure 2-547. Register 5Dh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 FB_ADC_CLK_
SYSREF_MUX
RX_ADC_CLK_
SYSREF_MUX
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-552. Register 5D Field Descriptions
Bit Field Type Reset Description
7-2 0 R/W 0h Must read or write 0
1-1
FB_ADC_CLK_SY
SREF_MUX
R/W 0h
Using fb clks by default
0 : use fb clk
1 : use rx clk
0-0
RX_ADC_CLK_SY
SREF_MUX
R/W 1h
Using fb clks by default
0 : use rx clk
1 : use fb clk
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