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Timing Controller Register Map
965
SBAU337–May 2020
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Serial Interface Register Maps
Table 2-2238. Register 93 Field Descriptions
Bit Field Type Reset Description
1-0
ENABLE_TX_GAIN
_SWAP_D
R/W 0h
Acts as an EN for txgswap for each bit of chD. If a bit of the
enable is 0, then the corresponding gain_swap bit will be
always 0.
2.15.17 Register 94h (offset = 94h) [reset = 0h]
Figure 2-2224. Register 94h
7 6 5 4 3 2 1 0
BROADCAST_
SWAP_TX
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2239. Register 94 Field Descriptions
Bit Field Type Reset Description
0-0
BROADCAST_SW
AP_TX
R/W 0h
Whether to broadcast tx_gain_swap from AB to CD or not. '0'
means no broadcast, '1' means broadcast
2.15.18 Register 95h (offset = 95h) [reset = 0h]
Figure 2-2225. Register 95h
7 6 5 4 3 2 1 0
ENABLE_TXDSALATCH
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2240. Register 95 Field Descriptions
Bit Field Type Reset Description
3-0
ENABLE_TXDSAL
ATCH
R/W 0h
These bits, when set, enable txdsalatch to take effect for that
channel. If made '0' then that channel's DSA gain will not be
updated on a +ve transition of txdsalatch signal
2.15.19 Register 98h (offset = 98h) [reset = 0h]
Figure 2-2226. Register 98h
7 6 5 4 3 2 1 0
BROADCAST_
TXNCOSEL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2241. Register 98 Field Descriptions
Bit Field Type Reset Description
0-0
BROADCAST_TXN
COSEL
R/W 0h
Setting this to '1' broadcasts to both TxAB and TxCD the
same ncosel.
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