Texas Instruments AFE79 Series - 2.5.49 Register 5 Ah (offset = 5 Ah) [reset = 15 h]

ADC JESD Register Map www.ti.com
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-549. Register 59 Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_JESD_CLK_
DIV2_RX1_P0
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
5-4
CTRL_JESD_CLK_
FB_P3
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
3-2
CTRL_JESD_CLK_
FB_P1
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
1-0
CTRL_JESD_CLK_
FB_P0
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
2.5.49 Register 5Ah (offset = 5Ah) [reset = 15h]
Figure 2-545. Register 5Ah
7 6 5 4 3 2 1 0
CTRL_JESD_CLK_RX1_P0_MS
F_RD
CTRL_JESD_CLK_DIV2_FB_P3 CTRL_JESD_CLK_DIV2_FB_P1 CTRL_JESD_CLK_DIV2_RX2_P
2
R/W-0h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-550. Register 5A Field Descriptions
Bit Field Type Reset Description
7-6
CTRL_JESD_CLK_
RX1_P0_MSF_RD
R/W 0h UNUSED
5-4
CTRL_JESD_CLK_
DIV2_FB_P3
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
3-2
CTRL_JESD_CLK_
DIV2_FB_P1
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled