Texas Instruments AFE79 Series - 2.3.87 Register 9 Fh (offset = 9 Fh) [reset = 20 h]; 2.3.88 Register A0 h (offset = A0 h) [reset = 2 h]

JESD_SUBCHIP Register Map www.ti.com
208
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.3.87 Register 9Fh (offset = 9Fh) [reset = 20h]
Figure 2-128. Register 9Fh
7 6 5 4 3 2 1 0
TX_OR_FB_CL
K_MUX
FB_CLK_DIV4_
COMMON_PH
ASE_DISABLE
FB_CLK_DIV4_
PHASE4_DISA
BLE
FB_CLK_DIV4_
PHASE3_DISA
BLE
FB_CLK_DIV4_
PHASE2_DISA
BLE
FB_CLK_DIV4_
PHASE1_DISA
BLE
FB_CLK_DIV4_
PHASE0_DISA
BLE
FB_CLK_DIV4_
MULTIPHASE_
DISABLE
R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-131. Register 9F Field Descriptions
Bit Field Type Reset Description
7-7
TX_OR_FB_CLK_
MUX
R/W 0h
selects fb_clk signals or tx_clk signals
0 : tx_clk
1 : fb_clk
6-6
FB_CLK_DIV4_CO
MMON_PHASE_DI
SABLE
R/W 0h
setting this to '1' will disable all clk-phases
0 : Enable
1 : Disable
5-5
FB_CLK_DIV4_PH
ASE4_DISABLE
R/W 1h
setting this to '1' will disable clock div8_phase4
0 : Enable
1 : Disable
4-4
FB_CLK_DIV4_PH
ASE3_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase3
0 : Enable
1 : Disable
3-3
FB_CLK_DIV4_PH
ASE2_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase2
0 : Enable
1 : Disable
2-2
FB_CLK_DIV4_PH
ASE1_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase1
0 : Enable
1 : Disable
1-1
FB_CLK_DIV4_PH
ASE0_DISABLE
R/W 0h
setting this to '1' will disable clock div8_phase0
0 : Enable
1 : Disable
0-0
FB_CLK_DIV4_MU
LTIPHASE_DISAB
LE
R/W 0h
0 - div8 clocks will have 4 clock-phases
1 - div8 clocks will have a single-phase
0 : Enable multi-phase
1 : Disable multi-phase
2.3.88 Register A0h (offset = A0h) [reset = 2h]
Figure 2-129. Register A0h
7 6 5 4 3 2 1 0
TX_CLK_LFSR
_SEED_LOAD
TX_CLK_SYSR
EF_VAL
TX_CLK_SYSR
EF_SEL
TX_CLK_SYSREF_DELAY TX_CLK_DITH
ERED_MODE_
EN
TX_CLK_DISA
BLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-132. Register A0 Field Descriptions
Bit Field Type Reset Description
7-7
TX_CLK_LFSR_SE
ED_LOAD
R/W 0h
Loads the LFSR seed value when this is set to 1. Need to be
used along with 'tx_clk_lfsr_seed_val' register
0 : Use default LFSR seed value
1 : Load LFSR seed value from register
6-6
TX_CLK_SYSREF
_VAL
R/W 0h spi-based sysref