Texas Instruments AFE79 Series - 2.5.122 Register B2 h (offset = B2 h) [reset = 0 h]; 2.5.123 Register B4 h (offset = B4 h) [reset = 0 h]; 2.5.124 Register B5 h (offset = B5 h) [reset = 0 h]

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Serial Interface Register Maps
Table 2-622. Register B0 Field Descriptions
Bit Field Type Reset Description
7-0 LINK2_RES2 R/W 0h JESD link config for STX 3,4/7,8
2.5.122 Register B2h (offset = B2h) [reset = 0h]
Figure 2-618. Register B2h
7 6 5 4 3 2 1 0
LINK2_JESD_I
LA_CONFIG_O
VERRIDE
0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-623. Register B2 Field Descriptions
Bit Field Type Reset Description
7-7
LINK2_JESD_ILA_
CONFIG_OVERRI
DE
R/W 0h
Config for STX 3,4/7,8
by default, JESD ILA parameters are defined from
JESD_MODE[7:0] settings when this bit is 0. mem_ila* are
dont care.
When 1, mem_link2_ila* registers are used to compute link
config
0 : Use functionally computed ILA LMFSN paramters
1 : Use ila* registers for ILA LMFSN parameters
6-0 0 R/W 0h Must read or write 0
2.5.123 Register B4h (offset = B4h) [reset = 0h]
Figure 2-619. Register B4h
7 6 5 4 3 2 1 0
LINK2_K_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-624. Register B4 Field Descriptions
Bit Field Type Reset Description
7-0 LINK2_K_M1 R/W 0h
Number of frames in a
multiframe, for STX 3,4/7,8
When link1_jesd_ila_config_override is 0,
this register is used as JESD link config for STX 3,4/7,8
2.5.124 Register B5h (offset = B5h) [reset = 0h]
Figure 2-620. Register B5h
7 6 5 4 3 2 1 0
0 0 0 0 LINK2_ENABL
E_F_CHAR_O
N_MFEND
LINK2_DISABL
E_F_CHAR
LINK2_DISABL
E_A_CHAR
LINK2_NO_LA
NE_SYNC
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset