Texas Instruments AFE79 Series - 2.5.186 Register 10 Ch (offset = 10 Ch) [reset = 0 h]; 2.5.187 Register 10 Dh (offset = 10 Dh) [reset = 0 h]; 2.5.188 Register 10 Eh (offset = 10 Eh) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-686. Register 10B Field Descriptions
Bit Field Type Reset Description
7-7 0 R/W 0h Must read or write 0
6-3
FB_JESD_RAMPT
EST_INCR
R/W 0h
Ramp step size is
1+register_value
Default value of this reg is 0, so ramp increments by 1
2-0
FB_JESD_TEST_S
IG_GEN_MODE
R/W 0h
Controls 0-7 fb streams
0 : No test
1 : short test
2 : ramp
4 : alt 0,1
2.5.186 Register 10Ch (offset = 10Ch) [reset = 0h]
Figure 2-682. Register 10Ch
7 6 5 4 3 2 1 0
JESD_SHORT_TEST_PATTERN_INPUT0[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-687. Register 10C Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORT_TE
ST_PATTERN_INP
UT0[7:0]
R/W 0h
Used when jesd_short_test_pattern_override or
fb_jesd_short_test_pattern_override are set
ADC sample0
2.5.187 Register 10Dh (offset = 10Dh) [reset = 0h]
Figure 2-683. Register 10Dh
7 6 5 4 3 2 1 0
JESD_SHORT_TEST_PATTERN_INPUT0[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-688. Register 10D Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORT_TE
ST_PATTERN_INP
UT0[15:8]
R/W 0h
Used when jesd_short_test_pattern_override or
fb_jesd_short_test_pattern_override are set
ADC sample0
2.5.188 Register 10Eh (offset = 10Eh) [reset = 0h]
Figure 2-684. Register 10Eh
7 6 5 4 3 2 1 0
JESD_SHORT_TEST_PATTERN_INPUT1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset