Texas Instruments AFE79 Series - 2.5.161 Register F2 h (offset = F2 h) [reset = 0 h]; 2.5.162 Register F3 h (offset = F3 h) [reset = 0 h]; 2.5.163 Register F4 h (offset = F4 h) [reset = 0 h]

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Serial Interface Register Maps
2.5.161 Register F2h (offset = F2h) [reset = 0h]
Figure 2-657. Register F2h
7 6 5 4 3 2 1 0
0 0 0 0 SERDES_FIFO_ERROR_DIFF2_MASK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-662. Register F2 Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-0
SERDES_FIFO_E
RROR_DIFF2_MA
SK
R/W 0h
By default if ptr spacing is 2, fifo errors are not raised. If
needed make this mask to 15.
3:0 bits - lane 3 to lane 0
2.5.162 Register F3h (offset = F3h) [reset = 0h]
Figure 2-658. Register F3h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 SERDES_FIFO
_PTR_SAMPL
E
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-663. Register F3 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
SERDES_FIFO_PT
R_SAMPLE
R/W 0h
When 1, internal fifo pointers are samples and save to the
registers:
serdes_fifo_wr_ptr_sample
serdes_fifo_rd_ptr_sample
2.5.163 Register F4h (offset = F4h) [reset = 0h]
Figure 2-659. Register F4h
7 6 5 4 3 2 1 0
ALARMS_SERDES_FIFO_ERRORS_UNMASKED ALARMS_SERDES_FIFO_ERRORS
R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-664. Register F4 Field Descriptions
Bit Field Type Reset Description
7-4
ALARMS_SERDES
_FIFO_ERRORS_
UNMASKED
R 0h
3-0
ALARMS_SERDES
_FIFO_ERRORS
R 0h
Error bits from jesd_tx_serdes_fifo (will go high for read or
write error)
[3]=STX4/8 jesd_tx_serdes_fifo error
[2]=STX3/7 jesd_tx_serdes_fifo error
[1]=STX2/6 jesd_tx_serdes_fifo error
[0]=STX1/5 jesd_tx_serdes_fifo error
This registers are un-affected by the mask bits