Texas Instruments AFE79 Series - 2.10.20 Register E8 h (offset = E8 h) [reset = 1 h]; 2.10.21 Register ECh (offset = ECh) [reset = 0 h]; 2.10.22 Register EDh (offset = EDh) [reset = 0 h]

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Serial Interface Register Maps
Table 2-1135. Register E4 Field Descriptions
Bit Field Type Reset Description
6-0
TM_PKDET_CUST
_EXTEND_TIME
R/W 8h
Customer peak detector extension in multiples of ADC_rate/32
clocks.
2.10.20 Register E8h (offset = E8h) [reset = 1h]
Figure 2-1126. Register E8h
7 6 5 4 3 2 1 0
NO_OVR_LNA
_BYP_WITH_S
WAP
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1136. Register E8 Field Descriptions
Bit Field Type Reset Description
0-0
NO_OVR_LNA_BY
P_WITH_SWAP
R/W 1h
If this bit is set, gain swap doesn't change LNA values.
However when this is zero, swapping change LNA settings to
swapped values.
2.10.21 Register ECh (offset = ECh) [reset = 0h]
Figure 2-1127. Register ECh
7 6 5 4 3 2 1 0
TM_GPIO_EXI
T
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1137. Register EC Field Descriptions
Bit Field Type Reset Description
0-0 TM_GPIO_EXIT R/W 0h
The GPIO exit bit that is written by customer to exit the
absolute reliability condition
2.10.22 Register EDh (offset = EDh) [reset = 0h]
Figure 2-1128. Register EDh
7 6 5 4 3 2 1 0
TM_GPIO_EXI
T_EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1138. Register ED Field Descriptions
Bit Field Type Reset Description
0-0
TM_GPIO_EXIT_E
N
R/W 0h enable GPIO based exit condition for absolute reliability