Texas Instruments AFE79 Series - 2.6.129 Register 49 E4 h (offset = 49 E4 h) [reset = 0 h]; 2.6.130 Register 49 E5 h (offset = 49 E5 h) [reset = Fh]; 2.6.131 Register 49 E6 h (offset = 49 E6 h) [reset = 10 h]; 2.6.132 Register 49 E8 h (offset = 49 E8 h) [reset = 40 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.6.129 Register 49E4h (offset = 49E4h) [reset = 0h]
Figure 2-843. Register 49E4h
7 6 5 4 3 2 1 0
TX_PLL_BIAS1
[0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-849. Register 49E4 Field Descriptions
Bit Field Type Reset Description
7-7 TX_PLL_BIAS1[0] R/W 0h Controls the TX PLL bias setting 1.
2.6.130 Register 49E5h (offset = 49E5h) [reset = Fh]
Figure 2-844. Register 49E5h
7 6 5 4 3 2 1 0
TX_PLL_BIAS2 TX_PLL_BIAS1[2:1]
R/W-3h R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-850. Register 49E5 Field Descriptions
Bit Field Type Reset Description
4-2 TX_PLL_BIAS2 R/W 3h Controls the TX PLL bias setting 2.
1-0
TX_PLL_BIAS1[2:1
]
R/W 3h Controls the TX PLL bias setting 1.
2.6.131 Register 49E6h (offset = 49E6h) [reset = 10h]
Figure 2-845. Register 49E6h
7 6 5 4 3 2 1 0
TX_PLL_VCO_
RANGE_MSB
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-851. Register 49E6 Field Descriptions
Bit Field Type Reset Description
4-4
TX_PLL_VCO_RA
NGE_MSB
R/W 1h
For PLL VCO range settings, see Register PzF4h: TX PLL
VCO RANGE LSB
2.6.132 Register 49E8h (offset = 49E8h) [reset = 40h]
Figure 2-846. Register 49E8h
7 6 5 4 3 2 1 0
VRVDD_TX
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset