Texas Instruments AFE79 Series - 2.4.131 Register A5 h (offset = A5 h) [reset = 0 h]; 2.4.132 Register A6 h (offset = A6 h) [reset = 0 h]

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Serial Interface Register Maps
Table 2-363. Register A4 Field Descriptions
Bit Field Type Reset Description
7-0 JESD_FS_STATE R 0h
JESDB: FS_STATE value
JESDC: UNUSED
bits(1:0) = SRX1/5
bits(3:2) = SRX2/6
bits(5:4) = SRX3/7
bits(7:6) = SRX4/8
For stable link (JESDB), the bits for each lane enabled should
read as "01"
Note: Refer to the TI application note for details on error
interpretation.
2.4.131 Register A5h (offset = A5h) [reset = 0h]
Figure 2-360. Register A5h
7 6 5 4 3 2 1 0
JESD_FS_STATE_PREV
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-364. Register A5 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_FS_STATE_
PREV
R 0h
JESDB: Previous FS_STATE value
JESDC: UNUSED
bits(1:0) = SRX1/5
bits(3:2) = SRX2/6
bits(5:4) = SRX3/7
bits(7:6) = SRX4/8
For stable link (JESDB), the bits for each lane enabled should
read as "00"
Note: Refer to the TI application note for details on error
interpretation.
2.4.132 Register A6h (offset = A6h) [reset = 0h]
Figure 2-361. Register A6h
7 6 5 4 3 2 1 0
JESD_BUF_STATE
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-365. Register A6 Field Descriptions
Bit Field Type Reset Description
7-0
JESD_BUF_STAT
E
R 0h
JESDB/C: ELASTIC_BUFFER_STATE value
bits(1:0) = SRX1/5
bits(3:2) = SRX2/6
bits(5:4) = SRX3/7
bits(7:6) = SRX4/8
For stable link, the bits for each lane enabled should read as
"11"
Note: Refer to the TI application note for details on error
interpretation.