Texas Instruments AFE79 Series - 2.4.94 Register 7 Dh (offset = 7 Dh) [reset = 0 h]; 2.4.95 Register 7 Eh (offset = 7 Eh) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-326. Register 7C Field Descriptions (continued)
Bit Field Type Reset Description
3-3
LINK1_FRAME_SY
NC_ERR_ENA
R/W 0h
JESDB: This bit select whether frame synchornization error
(generated due to continous K-characters in middle of data)
generated is counted in the err_count for the link. The bits
also control what signals are sent out the pad_syncb pin for
error notification.
2-2
LINK0_FRAME_SY
NC_ERR_ENA
R/W 0h
JESDB:This bit select whether frame synchornization error
(generated due to continous K-characters in middle of data)
generated is counted in the err_count for the link. The bits
also control what signals are sent out the pad_syncb pin for
error notification.
1-1
LINK1_FRAME_SY
NC_ERR_SYNC_R
EQUEST_ENA
R/W 1h
JESB : This bit selects whether frame synchornization error
(generated due to continous K-characters in middle of data)
causes a sync-request for lanes[2:3]/[6:7]. Sync requests take
priority over the error notification.
JESDC : This bit selects whether the 'fixed ones' error causes
a sync-request for lanes[2:3]/[6:7]
0-0
LINK0_FRAME_SY
NC_ERR_SYNC_R
EQUEST_ENA
R/W 1h
JESB : This bit selects whether frame synchornization error
(generated due to continous K-characters in middle of data)
causes a sync-request for lanes[0:1]/[4:5]. Sync requests take
priority over the error notification.
JESDC : This bit selects whether the 'fixed ones' error causes
a sync-request for lanes[0:1]/[4:5]
2.4.94 Register 7Dh (offset = 7Dh) [reset = 0h]
Figure 2-323. Register 7Dh
7 6 5 4 3 2 1 0
LINK0_LANE_ERROR_CNT_CLR
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-327. Register 7D Field Descriptions
Bit Field Type Reset Description
7-0
LINK0_LANE_ERR
OR_CNT_CLR
R/W 0h
These bits clear the error_counter for each of the errors
mentioned in sync_request_ena register for lanes[0:1]/[4:5].
2.4.95 Register 7Eh (offset = 7Eh) [reset = 0h]
Figure 2-324. Register 7Eh
7 6 5 4 3 2 1 0
LINK1_LANE_ERROR_CNT_CLR
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-328. Register 7E Field Descriptions
Bit Field Type Reset Description
7-0
LINK1_LANE_ERR
OR_CNT_CLR
R/W 0h
These bits clear the error_counter for each of the errors
mentioned in sync_request_ena register for lanes[2:3]/[6:7].