SERDES Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.6.88 Register 41EAh (offset = 41EAh) [reset = 30h]
Figure 2-802. Register 41EAh
7 6 5 4 3 2 1 0
VDRV_VDDR2[
0]
VDRV_VDDR3
R/W-0h R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-808. Register 41EA Field Descriptions
Bit Field Type Reset Description
7-7 VDRV_VDDR2[0] R/W 0h
6-4 VDRV_VDDR3 R/W 3h
2.6.89 Register 41EBh (offset = 41EBh) [reset = 8Fh]
Figure 2-803. Register 41EBh
7 6 5 4 3 2 1 0
PU_TX_LANE VDRV_VDDR1 VDRV_VDDR2[2:1]
R/W-1h R/W-3h R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-809. Register 41EB Field Descriptions
Bit Field Type Reset Description
7-7 PU_TX_LANE R/W 1h
Power up TX by lane.
0h: Power down
1h: Power up
4-2 VDRV_VDDR1 R/W 3h
1-0 VDRV_VDDR2[2:1] R/W 3h
2.6.90 Register 41ECh (offset = 41ECh) [reset = 0h]
Figure 2-804. Register 41ECh
7 6 5 4 3 2 1 0
MAIN_CURSOR
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-810. Register 41EC Field Descriptions
Bit Field Type Reset Description
7-5 MAIN_CURSOR R/W 0h
TX main-cursor setting
0h (000b) Main-cursor=MAIN-0
4h (100b) Main-cursor=MAIN-0.4
2h (010b) Main-cursor=MAIN-0.8
1h (001b) Main-cursor=MAIN-1.6