Texas Instruments AFE79 Series User Manual

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SBAU337–May 2020
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Serial Interface Register Maps
2.2.7 Register 63h (offset = 63h) [reset = 0h]
Figure 2-30. Register 63h
7 6 5 4 3 2 1 0
CLR_FLAG_LO
CK_OUT
CLR_FLAG_LO
CK_LOST
reserved reserved reserved
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-32. Register 63 Field Descriptions
Bit Field Type Reset Description
7-7
CLR_FLAG_LOCK
_OUT
R/W 0h clear LOCK sticky bit
6-6
CLR_FLAG_LOCK
_LOST
R/W 0h clear LOCK_LOST sticky bit
5-5 reserved R/W 0h
4-4 reserved R/W 0h
3-0 reserved R/W 0h
2.2.8 Register 66h (offset = 66h) [reset = 0h]
Figure 2-31. Register 66h
7 6 5 4 3 2 1 0
LOCK_LOST_S
TICKY
LOCK_OUT_S
TICKY
LOCK reserved reserved EN_LOCK_DE
TECT
EN_CAL
R-0h R-0h R-0h R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-33. Register 66 Field Descriptions
Bit Field Type Reset Description
6-6
LOCK_LOST_STIC
KY
R 0h
This register is set to 1 when PLL loses lock after initial lock is
obtained. Indicates whether the PLL lock is lost anytime after
initial lock.
1 : PLL lock lost
0 : PLL lock not lost.
Can be reset by CLR_FLAG_LOCK_LOST
5-5
LOCK_OUT_STIC
KY
R 0h
This register is set to 1 when PLL locks and is sticky.
1: PLL locked. Is sticky.
0: PLL not locked.
Can be reset with CLR_FLAG_LOCK_OUT
4-4 LOCK R 0h
Active PLL lock signal. Provides PLL lock status in real time. It
is not a sticky bit
1: PLL is locked.
0: PLL not locked.
3-3 reserved R 0h
2-2 reserved R/W 0h
1-1
EN_LOCK_DETEC
T
R/W 0h
Enable the lock detection for PLL
0 -> Disabled
1 -> enabled.
0-0 EN_CAL R/W 0h
Register to calibrate PLL. A rising edge(0 to 1 transition on
this register) is required to calibrate the PLL.

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English