ADC JESD Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-565. Register 6D Field Descriptions (continued)
Bit Field Type Reset Description
1-1
LINK1_INIT_STAT
E
R/W 1h
To control STX2/6
0 : JESD in non-reset state
1 : JESD is in reset state
0-0
LINK0_INIT_STAT
E
R/W 1h
To control STX1/5
0 : JESD in non-reset state
1 : JESD is in reset state
2.5.65 Register 6Eh (offset = 6Eh) [reset = Fh]
Figure 2-561. Register 6Eh
7 6 5 4 3 2 1 0
0 0 0 0 LANE3_SERD
ES_FIFO_INIT
_STATE
LANE2_SERD
ES_FIFO_INIT
_STATE
LANE1_SERD
ES_FIFO_INIT
_STATE
LANE0_SERD
ES_FIFO_INIT
_STATE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-566. Register 6E Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LANE3_SERDES_
FIFO_INIT_STATE
R/W 1h
Used to reset STX4/8, serdes fifo when
init_state_serdesfifo_spi_ovr = 1
2-2
LANE2_SERDES_
FIFO_INIT_STATE
R/W 1h
Used to reset STX3/7, serdes fifo when
init_state_serdesfifo_spi_ovr = 1
1-1
LANE1_SERDES_
FIFO_INIT_STATE
R/W 1h
Used to reset STX2/6, serdes fifo when
init_state_serdesfifo_spi_ovr = 1
0-0
LANE0_SERDES_
FIFO_INIT_STATE
R/W 1h
Used to reset STX1/5, serdes fifo when
init_state_serdesfifo_spi_ovr = 1
2.5.66 Register 6Fh (offset = 6Fh) [reset = 2h]
Figure 2-562. Register 6Fh
7 6 5 4 3 2 1 0
0 0 0 0 0 INIT_STATE_S
ERDESFIFO_S
PI_OVR
INIT_STATE_G
EARBOX_SPI_
OVR
0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-567. Register 6F Field Descriptions
Bit Field Type Reset Description
7-3 0 R/W 0h Must read or write 0
2-2
INIT_STATE_SER
DESFIFO_SPI_OV
R
R/W 0h
If 1:
serdes fifo is reset using link*_serdes_fifo_init_state
else:
serdes fifo is reset with sysref aligned link_init_state
1-1
INIT_STATE_GEA
RBOX_SPI_OVR
R/W 1h
Should be 1
If 1:
link_fifo_init_state register is inteneded for reset
else:
gearbox is reset with sysref aligned link_init_state.
0-0 0 R/W 0h Must read or write 0