Texas Instruments AFE79 Series - 2.5.104 Register 9 Eh (offset = 9 Eh) [reset = 1 h]; 2.5.105 Register 9 Fh (offset = 9 Fh) [reset = 0 h]

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Serial Interface Register Maps
Table 2-604. Register 9D Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LINK1_ENABLE_F
_CHAR_ON_MFE
ND
R/W 0h
Config for STX2/6
By default, don't send f_char on multiframe_end.
When 1, f_char is sen't on multiframe_end
2-2
LINK1_DISABLE_F
_CHAR
R/W 0h
Config for STX2/6
Disable character replacement with CTRL_F for JESD-B
1-1
LINK1_DISABLE_A
_CHAR
R/W 0h
Config for STX2/6
Disable character replacement with CTRL_A for JESD-B
0-0
LINK1_NO_LANE_
SYNC
R/W 0h
Config for STX2/6
Set if lane synchronization is not supported. When set, ILA is
not transmitted
2.5.104 Register 9Eh (offset = 9Eh) [reset = 1h]
Figure 2-600. Register 9Eh
7 6 5 4 3 2 1 0
0 0 0 0 LINK1_SYNC_
F_CTR_INCR_
OVR_EN
LINK1_SYNC_F_CTR_INCR_OVR_VAL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-605. Register 9E Field Descriptions
Bit Field Type Reset Description
7-4 0 R/W 0h Must read or write 0
3-3
LINK1_SYNC_F_C
TR_INCR_OVR_E
N
R/W 0h
Config for STX2/6
To ovr, sync_n low duration check
2-0
LINK1_SYNC_F_C
TR_INCR_OVR_V
AL
R/W 1h
Config for STX2/6
When link1_sync_f_ctr_incr_ovr_en, sync_n low duration
counter is incremented with this spi value.
Can be 1 or 2 or 4
This value is used a steps to increment sync_f counter which
checks sync inactive width of 4 or more
2.5.105 Register 9Fh (offset = 9Fh) [reset = 0h]
Figure 2-601. Register 9Fh
7 6 5 4 3 2 1 0
0 0 0 0 0 LINK1_JESD_TEST_SEQ_SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset