IO Wrap Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.16.565 Register A48h (offset = A48h) [reset = 0h]
Figure 2-2828. Register A48h
7 6 5 4 3 2 1 0
SEL_INTPI_TX_NCOSEL_3 POL_INTPI_TX
_NCOSEL_3
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2844. Register A48 Field Descriptions
Bit Field Type Reset Description
2-1
SEL_INTPI_TX_N
COSEL_3
R/W 0h
select control for intpi_tx_ncosel_3. 0 indicates take from
parallel GPIO 1 indicates take from Serial LVDS GPIO 2
indicates take from Serdes GPIO
0-0
POL_INTPI_TX_N
COSEL_3
R/W 0h
polarity control for intpi_tx_ncosel_3. 0 indicates pass through
from GPIO when selected 1 indicates inverted signal
2.16.566 Register A49h (offset = A49h) [reset = 2h]
Figure 2-2829. Register A49h
7 6 5 4 3 2 1 0
OVR_SEL_INT
PI_TX_NCOSE
L_3
OVR_INTPI_TX
_NCOSEL_3
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2845. Register A49 Field Descriptions
Bit Field Type Reset Description
1-1
OVR_SEL_INTPI_
TX_NCOSEL_3
R/W 1h
control to select whether the input function intpi_tx_ncosel_3
needs to be overriden ot not. 1 indicates override.
0-0
OVR_INTPI_TX_N
COSEL_3
R/W 0h override value for ovr_sel_intpi_tx_ncosel_3 is made high
2.16.567 Register F00h (offset = F00h) [reset = 0h]
Figure 2-2830. Register F00h
7 6 5 4 3 2 1 0
USE_SERIAL_
GPIO
reserved reserved reserved reserved
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2846. Register F00 Field Descriptions
Bit Field Type Reset Description
4-4
USE_SERIAL_GPI
O
R/W 0h Enables Serial GPIO mode controlling GPIO
3-3 reserved R/W 0h
2-2 reserved R/W 0h
1-1 reserved R/W 0h
0-0 reserved R/W 0h