SERDES Register Map
www.ti.com
492
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-801. Register 4141 Field Descriptions (continued)
Bit Field Type Reset Description
5-5 TX_TEST_EN R/W 0h
Mux control bit to select whether the TX sends out user data
or test data.
0h: User data
1h: Test data
4-4
LOOPBACK_CLO
CK_INV
R/W 0h
3-3
TX_PRBS_GEN_E
N
R/W 0h
Enables the TX PRBS generator logic.
0h: Disabled
1h: Enabled
2-2
TX_PRBS_GEN_E
RR
R/W 0h
Setting this bit will generate a single bit flip in the PRBS
generated output. To send additional error(s), the bit must be
cleared first.
1-0 TX_PRBS_MODE R/W 0h
PRBS mode select of the TX PRBS generator.
0h: PRBS9
1h: PRBS15
2h: PRBS23
3h: PRBS31
2.6.82 Register 4142h (offset = 4142h) [reset = AAh]
Figure 2-796. Register 4142h
7 6 5 4 3 2 1 0
TX_TEST_PATTERN_HIGH[7:0]
R/W-AAh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-802. Register 4142 Field Descriptions
Bit Field Type Reset Description
7-0
TX_TEST_PATTE
RN_HIGH[7:0]
R/W AAh Upper word of the 32-bit TX test pattern memory.
2.6.83 Register 4143h (offset = 4143h) [reset = AAh]
Figure 2-797. Register 4143h
7 6 5 4 3 2 1 0
TX_TEST_PATTERN_HIGH[15:8]
R/W-AAh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-803. Register 4143 Field Descriptions
Bit Field Type Reset Description
7-0
TX_TEST_PATTE
RN_HIGH[15:8]
R/W AAh Upper word of the 32-bit TX test pattern memory.
2.6.84 Register 4144h (offset = 4144h) [reset = AAh]
Figure 2-798. Register 4144h
7 6 5 4 3 2 1 0
TX_TEST_PATTERN_LOW[7:0]
R/W-AAh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset