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SERDES Register Map
495
SBAU337–May 2020
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Serial Interface Register Maps
2.6.91 Register 41EDh (offset = 41EDh) [reset = 0h]
Figure 2-805. Register 41EDh
7 6 5 4 3 2 1 0
POST_CURSOR PRE_CURSOR
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-811. Register 41ED Field Descriptions
Bit Field Type Reset Description
5-3 POST_CURSOR R/W 0h
TX post-cursor setting
0h (000b) Post-cursor=0
4h (100b) Post-cursor=0.4
2h (010b) Post-cursor=0.8
1h (001b) Post-cursor=1.6
2-0 PRE_CURSOR R/W 0h
TX pre-cursor setting
0h (000b) Pre-cursor=0
4h (100b) Pre-cursor=0.4
2h (010b) Pre-cursor=0.8
1h (001b) Pre-cursor=1.6
2.6.92 Register 41EEh (offset = 41EEh) [reset = 0h]
Figure 2-806. Register 41EEh
7 6 5 4 3 2 1 0
TESTMODE_R
X[0]
VTSTGRPU_RX ENTSTPGROU
P_RX
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-812. Register 41EE Field Descriptions
Bit Field Type Reset Description
7-7 TESTMODE_RX[0] R/W 0h
6-1 VTSTGRPU_RX R/W 0h
0-0
ENTSTPGROUP_
RX
R/W 0h
2.6.93 Register 41EFh (offset = 41EFh) [reset = 0h]
Figure 2-807. Register 41EFh
7 6 5 4 3 2 1 0
TESTMODE_RX[2:1]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-813. Register 41EF Field Descriptions
Bit Field Type Reset Description
1-0
TESTMODE_RX[2:
1]
R/W 0h