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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-1969. Register 40C Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_PWR_AT
TACK_STEP_SIZE
R/W 2h
Gain step when Digital power detector attack is triggered. 0.5
dB step size.
2.14.73 Register 40Dh (offset = 40Dh) [reset = 2h]
Figure 2-1956. Register 40Dh
7 6 5 4 3 2 1 0
FB_AGC_PWR_DECAY_STEP_SIZE
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1970. Register 40D Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_PWR_D
ECAY_STEP_SIZE
R/W 2h
Gain step when Digital power detector decay is triggered. 0.5
dB step size.
2.14.74 Register 410h (offset = 410h) [reset = Ch]
Figure 2-1957. Register 410h
7 6 5 4 3 2 1 0
FB_AGC_LNARF_ATTACK_STEP_SIZE
R/W-Ch
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1971. Register 410 Field Descriptions
Bit Field Type Reset Description
5-0
FB_AGC_LNARF_
ATTACK_STEP_SI
ZE
R/W Ch Gain step when RF attack is triggered. 0.5 dB step size.
2.14.75 Register 414h (offset = 414h) [reset = 0h]
Figure 2-1958. Register 414h
7 6 5 4 3 2 1 0
FB_AGC_BIG_STEP_ATTACK_WIN_LEN[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-1972. Register 414 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BIG_STE
P_ATTACK_WIN_L
EN[7:0]
R/W 0h
Digital big step attack det window length. Max supported
length is 2^24 - 2.