Texas Instruments AFE79 Series - 2.5.101 Register 9 Bh (offset = 9 Bh) [reset = 0 h]; 2.5.102 Register 9 Ch (offset = 9 Ch) [reset = 0 h]; 2.5.103 Register 9 Dh (offset = 9 Dh) [reset = 0 h]

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Serial Interface Register Maps
Table 2-601. Register 98 Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_RES2 R/W 0h JESD link config for STX2/6
2.5.101 Register 9Bh (offset = 9Bh) [reset = 0h]
Figure 2-597. Register 9Bh
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 LINK1_JESD_I
LA_CONFIG_O
VERRIDE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-602. Register 9B Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
LINK1_JESD_ILA_
CONFIG_OVERRI
DE
R/W 0h
Controls STX2/6
by default, JESD ILA parameters are defined from
JESD_MODE[7:0] settings when this bit is 0. mem_ila* are
dont care.
When 1, mem_link1_ila* registers are used to compute link
config
0 : Use functionally computed ILA LMFSN paramters
1 : Use ila* registers for ILA LMFSN parameters
2.5.102 Register 9Ch (offset = 9Ch) [reset = 0h]
Figure 2-598. Register 9Ch
7 6 5 4 3 2 1 0
LINK1_K_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-603. Register 9C Field Descriptions
Bit Field Type Reset Description
7-0 LINK1_K_M1 R/W 0h
Number of frames in a
multiframe, for STX2/6
When link1_jesd_ila_config_override is 0,
this register is used as JESD link config for STX2/6
2.5.103 Register 9Dh (offset = 9Dh) [reset = 0h]
Figure 2-599. Register 9Dh
7 6 5 4 3 2 1 0
0 0 0 0 LINK1_ENABL
E_F_CHAR_O
N_MFEND
LINK1_DISABL
E_F_CHAR
LINK1_DISABL
E_A_CHAR
LINK1_NO_LA
NE_SYNC
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset