Texas Instruments AFE79 Series - 2.7 ANA_4 T4 R Register Map; 2.7.1 Register 10 Ch (offset = 10 Ch) [reset = 0 h]; 2.7.2 Register 10 Dh (offset = 10 Dh) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.7 ANA_4T4R Register Map
Table 2-928. ana_4t4r Register Map
ADDRESS (Hex) D7 D6 D5 D4 D3 D2 D1 D0
10Ch 0 0 0 0 0 0 0
EN_REFDIV_DM
P
10Dh 0 0 0 CTL_REFDIV_DIV
10Eh 0 0 0 0 0 0 0
CTL_FBDIV_DIV
BY2
10Fh 0 CTL_FBDIV_DIV
110h 0 0 0 0 0 0 CTL_OUTDIV_MUX_TX
111h 0 0 0 0 0 CTL_OUTDIV_DIV_TX
112h 0 0 0 0 0 0 CTL_OUTDIV_MUX_RX
113h 0 0 0 0 0 CTL_OUTDIV_DIV_RX
114h 0 0 0 0 0 0 CTL_OUTDIV_MUX_FB
115h 0 0 0 0 0 CTL_OUTDIV_DIV_FB
2.7.1 Register 10Ch (offset = 10Ch) [reset = 0h]
Figure 2-922. Register 10Ch
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 EN_REFDIV_D
MP
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-929. Register 10C Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0 EN_REFDIV_DMP R/W 0h
reference clock divider. Need to be engaged only if reference
clock frequnecy > 8X (500Mhz).
2.7.2 Register 10Dh (offset = 10Dh) [reset = 0h]
Figure 2-923. Register 10Dh
7 6 5 4 3 2 1 0
0 0 0 CTL_REFDIV_DIV
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-930. Register 10D Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0 CTL_REFDIV_DIV R/W 0h
reference divider. Need to be engaged iff ref-freq > 8X
(500Mhz).