Texas Instruments AFE79 Series - 2.4.71 Register 66 h (offset = 66 h) [reset = 4 h]; 2.4.72 Register 67 h (offset = 67 h) [reset = 4 h]; 2.4.73 Register 68 h (offset = 68 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-303. Register 65 Field Descriptions
Bit Field Type Reset Description
3-0
K_COUNTER_THR
ESH
R/W 4h
JESDB:k-counter threshold for Code-group synchronization
JESDC : UNUSED
2.4.71 Register 66h (offset = 66h) [reset = 4h]
Figure 2-300. Register 66h
7 6 5 4 3 2 1 0
V_COUNTER_THRESH
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-304. Register 66 Field Descriptions
Bit Field Type Reset Description
3-0
V_COUNTER_THR
ESH
R/W 4h
JESDB:valid counter threshold for Code-group
synchronization
JESDC : UNUSED
2.4.72 Register 67h (offset = 67h) [reset = 4h]
Figure 2-301. Register 67h
7 6 5 4 3 2 1 0
I_COUNTER_THRESH
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-305. Register 67 Field Descriptions
Bit Field Type Reset Description
3-0
I_COUNTER_THR
ESH
R/W 4h
JESDB:invalid counter threshold for Code-group
synchronization
JESDC : UNUSED
2.4.73 Register 68h (offset = 68h) [reset = 0h]
Figure 2-302. Register 68h
7 6 5 4 3 2 1 0
LINK0_RBD_M1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-306. Register 68 Field Descriptions
Bit Field Type Reset Description
7-0
LINK0_RBD_M1[7:
0]
R/W 0h
This is the number of clock cycles(one clock cycle freq =
LaneRate/40 for JESDB or LaneRate/33 for JESDC) to
release the data from the JESD RBD buffers if all the /R
characters(JESDB) or EMB lock(JESDC) across the used
lanes have arrived for lanes[0:1]/lanes[4:5].
JESDB: Max value is F*K/4-1
JESDC: Max value is 64*E-1