Texas Instruments AFE79 Series User Manual

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520
SBAU337–May 2020
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Serial Interface Register Maps
2.6.167 Register 702Dh (offset = 702Dh) [reset = 0h]
Figure 2-881. Register 702Dh
7 6 5 4 3 2 1 0
CMD_PARAM_OR_STATUSB[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-887. Register 702D Field Descriptions
Bit Field Type Reset Description
7-0
CMD_PARAM_OR
_STATUSB[15:8]
R/W 0h Command Parameter / Status
2.6.168 Register 702Fh (offset = 702Fh) [reset = 0h]
Figure 2-882. Register 702Fh
7 6 5 4 3 2 1 0
SRAM_BIST_E
N
SRAM_BIST_S
TART
ROM_BIST_CL
K_EN
ROM_BIST_EN
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-888. Register 702F Field Descriptions
Bit Field Type Reset Description
7-7 SRAM_BIST_EN R/W 0h Enter SRAM BIST mode. Prepare for BIST.
6-6
SRAM_BIST_STA
RT
R/W 0h SRAM BIST start.
5-5
ROM_BIST_CLK_
EN
R/W 0h
ROM BIST Clock Gate.
0h: Disable
1h: Enable
4-4 ROM_BIST_EN R/W 0h
ROM BIST Test Enable.
0h: Disable
1h: Enable
2.6.169 Register 7031h (offset = 7031h) [reset = 0h]
Figure 2-883. Register 7031h
7 6 5 4 3 2 1 0
SRAM_BIST_D
ONE
SRAM_BIST_P
ASS
ROM_BIST_D
ONE
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-889. Register 7031 Field Descriptions
Bit Field Type Reset Description
7-7
SRAM_BIST_DON
E
R 0h
SRAM BIST process completed.
1h: Completed.
6-6
SRAM_BIST_PAS
S
R 0h
SRAM BIST passed or failed:
0h: Fail
1h: Pass
5-5 ROM_BIST_DONE R 0h
ROM BIST process completed.
1h: Completed.

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English