Timing Controller Register Map
www.ti.com
972
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
2.15.40 Register B2h (offset = B2h) [reset = 0h]
Figure 2-2247. Register B2h
7 6 5 4 3 2 1 0
ENABLE_RXNCOSEL_C
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2262. Register B2 Field Descriptions
Bit Field Type Reset Description
4-0
ENABLE_RXNCOS
EL_C
R/W 0h
If enable == 0 then the corresponding bit in rxncosel for that
channel is made 0, else ncosel is sent as it is
2.15.41 Register B3h (offset = B3h) [reset = 0h]
Figure 2-2248. Register B3h
7 6 5 4 3 2 1 0
ENABLE_RXNCOSEL_D
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2263. Register B3 Field Descriptions
Bit Field Type Reset Description
4-0
ENABLE_RXNCOS
EL_D
R/W 0h
If enable == 0 then the corresponding bit in rxncosel for that
channel is made 0, else ncosel is sent as it is
2.15.42 Register B5h (offset = B5h) [reset = 0h]
Figure 2-2249. Register B5h
7 6 5 4 3 2 1 0
ENABLE_FB_GAIN_SWAP_AB
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2264. Register B5 Field Descriptions
Bit Field Type Reset Description
1-0
ENABLE_FB_GAIN
_SWAP_AB
R/W 0h
Acts as a enable for gain swap for the fbab channel. If a bit is
1, then the corresponding rxgswap bit is used, else it is made
0. For eg '11' uses both bits of rxgswap as fbgswap. '10' uses
only MSB of rxgswap for fbgswap etc
2.15.43 Register B6h (offset = B6h) [reset = 0h]
Figure 2-2250. Register B6h
7 6 5 4 3 2 1 0
ENABLE_FB_GAIN_SWAP_CD
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
To Next Page
Loading...
Need help?
General
