Texas Instruments AFE79 Series - 2.4.14 Register 2 Dh (offset = 2 Dh) [reset = 0 h]; 2.4.15 Register 2 Eh (offset = 2 Eh) [reset = 1 h]; 2.4.16 Register 2 Fh (offset = 2 Fh) [reset = 0 h]

DAC JESD Register Map www.ti.com
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SBAU337–May 2020
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Serial Interface Register Maps
2.4.14 Register 2Dh (offset = 2Dh) [reset = 0h]
Figure 2-243. Register 2Dh
7 6 5 4 3 2 1 0
ROOT_CLK_TX1_DIV_N_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-247. Register 2D Field Descriptions
Bit Field Type Reset Description
4-0
ROOT_CLK_TX1_
DIV_N_M1
R/W 0h
For lanes[0:1]/[4:5], N_M1 value in Divide ratio of M/N for
generating the root-clock for DAC_JESD from 48x clock. All
the other internal clocks like DUC_WR_CLK and
JESD_RX_CLK are derieved from this root clock
2.4.15 Register 2Eh (offset = 2Eh) [reset = 1h]
Figure 2-244. Register 2Eh
7 6 5 4 3 2 1 0
ROOT_CLK_TX2_DIV_M
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-248. Register 2E Field Descriptions
Bit Field Type Reset Description
4-0
ROOT_CLK_TX2_
DIV_M
R/W 1h
For lanes[2:3]/[6:7], M-value in Divide ratio of M/N for
generating the root-clock for DAC_JESD from 48x clock. All
the other internal clocks like DUC_WR_CLK and
JESD_RX_CLK are derieved from this root clock
2.4.16 Register 2Fh (offset = 2Fh) [reset = 0h]
Figure 2-245. Register 2Fh
7 6 5 4 3 2 1 0
ROOT_CLK_TX2_DIV_N_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-249. Register 2F Field Descriptions
Bit Field Type Reset Description
4-0
ROOT_CLK_TX2_
DIV_N_M1
R/W 0h
For lanes[2:3]/[6:7], N_M1 in value in Divide ratio of M/N for
generating the root-clock for DAC_JESD from 48x clock. All
the other internal clocks like DUC_WR_CLK and
JESD_RX_CLK are derieved from this root clock