Texas Instruments AFE79 Series - 2.3.118 Register C8 h (offset = C8 h) [reset = 0 h]; 2.3.119 Register C9 h (offset = C9 h) [reset = 0 h]

JESD_SUBCHIP Register Map www.ti.com
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SBAU337–May 2020
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Serial Interface Register Maps
2.3.118 Register C8h (offset = C8h) [reset = 0h]
Figure 2-159. Register C8h
7 6 5 4 3 2 1 0
DAC_JESD_SY
NC_N3_SPI_O
VR
DAC_JESD_SY
NC_N3_SPI_V
AL
DAC_JESD_SY
NC_N2_SPI_O
VR
DAC_JESD_SY
NC_N2_SPI_V
AL
DAC_JESD_SY
NC_N1_SPI_O
VR
DAC_JESD_SY
NC_N1_SPI_V
AL
DAC_JESD_SY
NC_N0_SPI_O
VR
DAC_JESD_SY
NC_N0_SPI_V
AL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-162. Register C8 Field Descriptions
Bit Field Type Reset Description
7-7
DAC_JESD_SYNC
_N3_SPI_OVR
R/W 0h
Override the dac_jesd sync_n3 pin going out with
dac_jesd_sync_n3_spi_val
6-6
DAC_JESD_SYNC
_N3_SPI_VAL
R/W 0h
spi-based dac_jesd sync_n0 which overrides the pin sync_n3.
Need to be used along with 'dac_jesd_sync_n3_spi_ovr'
register.
5-5
DAC_JESD_SYNC
_N2_SPI_OVR
R/W 0h
Override the dac_jesd sync_n2 pin going out with
dac_jesd_sync_n2_spi_val
4-4
DAC_JESD_SYNC
_N2_SPI_VAL
R/W 0h
spi-based dac_jesd sync_n0 which overrides the pin sync_n2.
Need to be used along with 'dac_jesd_sync_n2_spi_ovr'
register.
3-3
DAC_JESD_SYNC
_N1_SPI_OVR
R/W 0h
Override the dac_jesd sync_n1 pin going out with
dac_jesd_sync_n1_spi_val
2-2
DAC_JESD_SYNC
_N1_SPI_VAL
R/W 0h
spi-based dac_jesd sync_n0 which overrides the pin sync_n1.
Need to be used along with 'dac_jesd_sync_n1_spi_ovr'
register.
1-1
DAC_JESD_SYNC
_N0_SPI_OVR
R/W 0h
Override the dac_jesd sync_n0 pin going out with
dac_jesd_sync_n0_spi_val
0-0
DAC_JESD_SYNC
_N0_SPI_VAL
R/W 0h
spi-based dac_jesd sync_n0 which overrides the pin sync_n0.
Need to be used along with 'dac_jesd_sync_n0_spi_ovr'
register.
2.3.119 Register C9h (offset = C9h) [reset = 0h]
Figure 2-160. Register C9h
7 6 5 4 3 2 1 0
DAC_JESD_SY
NC_N3_INV
DAC_JESD_SY
NC_N2_INV
DAC_JESD_SY
NC_N1_INV
DAC_JESD_SY
NC_N0_INV
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-163. Register C9 Field Descriptions
Bit Field Type Reset Description
3-3
DAC_JESD_SYNC
_N3_INV
R/W 0h
Invert dac_jesd sync_n2 output
0 : No-invert
1 : Invert
2-2
DAC_JESD_SYNC
_N2_INV
R/W 0h
Invert dac_jesd sync_n2 output
0 : No-invert
1 : Invert
1-1
DAC_JESD_SYNC
_N1_INV
R/W 0h
Invert dac_jesd sync_n1 output
0 : No-invert
1 : Invert
0-0
DAC_JESD_SYNC
_N0_INV
R/W 0h
Invert dac_jesd sync_n0 output
0 : No-invert
1 : Invert