Timing Controller Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-2222. tg_top Register Map (continued)
ADDRESS (Hex) D7 D6 D5 D4 D3 D2 D1 D0
BAh FORCE_FBNCOSEL_CD
BCh ENABLE_FBNCOSEL_AB
BDh ENABLE_FBNCOSEL_CD
C0h DUAL_FBMODE
C1h
SINGLEFB_CHA
_CHC
C2h CH0_LSB_FBMUXSEL
C3h CH1_LSB_FBMUXSEL
C4h CH0_MSB_FBMUXSEL
C5h CH1_MSB_FBMUXSEL
C6h OVERRIDE_FBMUXSEL
C7h OVERRIDE_VAL_FBMUXSEL
2.15.1 Register 80h (offset = 80h) [reset = 0h]
Figure 2-2208. Register 80h
7 6 5 4 3 2 1 0
MODE_2T2R
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2223. Register 80 Field Descriptions
Bit Field Type Reset Description
0-0 MODE_2T2R R/W 0h
mode_2t2r==1 -> Controls for AB side and CD side are
independent
mode_2t2r==0 -> Controls for channel A are broadcast to all 4
channels.
This control takes effect for both Tx and Rx Enables.
System normally comes up with this bit=1
2.15.2 Register 81h (offset = 81h) [reset = 1h]
Figure 2-2209. Register 81h
7 6 5 4 3 2 1 0
FDD_MODE
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2224. Register 81 Field Descriptions
Bit Field Type Reset Description
0-0 FDD_MODE R/W 1h
fdd_mode==1 -> Complete system is in FDD mode. Allows
independent Rx and Fb enables.
fdd_mode==0 -> Atleast one-side (either AB or CD) is in TDD
mode. Allows Rx and Fb chains to be shared and in that case
rxa/b/c/d_fb_shr should be programmed appropriately
System normally comes up with fdd_mode=0
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