SERDES Register Map
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SBAU337–May 2020
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Serial Interface Register Maps
2.6.62 Register 4095h (offset = 4095h) [reset = 8h]
Figure 2-776. Register 4095h
7 6 5 4 3 2 1 0
PHASE_WAND
ER_LEVEL_SE
L
TOP_ROTATO
R_EN
RX_SPEED_SEL[2:1]
R/W-1h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-782. Register 4095 Field Descriptions
Bit Field Type Reset Description
3-3
PHASE_WANDER
_LEVEL_SEL
R/W 1h Enable the frequency accumulator to top rotator.
2-2
TOP_ROTATOR_E
N
R/W 0h Enable the frequency accumulator on local phase increment.
1-0
RX_SPEED_SEL[2
:1]
R/W 0h
RX speed select
0h: Full-rate
4h: Half-rate
5h: Quarter-rate
6h: Eighth-rate
7h: Sixteenth-rate
2.6.63 Register 4096h (offset = 4096h) [reset = 0h]
Figure 2-777. Register 4096h
7 6 5 4 3 2 1 0
EDGE3[1:0] EDGE2 EDGE1
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-783. Register 4096 Field Descriptions
Bit Field Type Reset Description
7-6 EDGE3[1:0] R/W 0h Timing loop Phase 3 edge delay.
5-3 EDGE2 R/W 0h Timing loop Phase 2 edge delay.
2-0 EDGE1 R/W 0h Timing loop Phase 1 edge delay.
2.6.64 Register 4097h (offset = 4097h) [reset = 0h]
Figure 2-778. Register 4097h
7 6 5 4 3 2 1 0
PH_WAND_CL
K_EN
EDGE4 EDGE3[2]
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-784. Register 4097 Field Descriptions
Bit Field Type Reset Description
7-7
PH_WAND_CLK_E
N
R/W 0h Enable phase wander clock.
3-1 EDGE4 R/W 0h Timing loop Phase 4 edge delay.
0-0 EDGE3[2] R/W 0h Timing loop Phase 3 edge delay.