Texas Instruments AFE79 Series - 2.4.12 Register 2 Bh (offset = 2 Bh) [reset = 0 h]; 2.4.13 Register 2 Ch (offset = 2 Ch) [reset = 1 h]

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Serial Interface Register Maps
Table 2-244. Register 2A Field Descriptions
Bit Field Type Reset Description
3-2
MAPPER_SYNC_F
IFO_TX4_OFFSET
_VAL
R/W 2h
set mapper sync-fifo offset through this register.To be used
along with mapper_sync_fifo_tx4_offset_ovr.
1-0
MAPPER_SYNC_F
IFO_TX3_OFFSET
_VAL
R/W 2h
set mapper sync-fifo offset through this register.To be used
along with mapper_sync_fifo_tx3_offset_ovr.
2.4.12 Register 2Bh (offset = 2Bh) [reset = 0h]
Figure 2-241. Register 2Bh
7 6 5 4 3 2 1 0
MAPPER_SYN
C_FIFO_TX4_
MODE_VAL
MAPPER_SYN
C_FIFO_TX3_
MODE_VAL
MAPPER_SYNC_FIFO_TX2_MODE_VAL MAPPER_SYNC_FIFO_TX1_MODE_VAL
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-245. Register 2B Field Descriptions
Bit Field Type Reset Description
7-7
MAPPER_SYNC_F
IFO_TX4_MODE_
VAL
R/W 0h UNUSED
6-6
MAPPER_SYNC_F
IFO_TX3_MODE_
VAL
R/W 0h UNUSED
5-3
MAPPER_SYNC_F
IFO_TX2_MODE_
VAL
R/W 0h
set mapper sync-fifo mode through this register. To be used
along with mapper_sync_fifo_tx2_mode_ovr.
2-0
MAPPER_SYNC_F
IFO_TX1_MODE_
VAL
R/W 0h
set mapper sync-fifo mode through this register. To be used
along with mapper_sync_fifo_tx1_mode_ovr.
2.4.13 Register 2Ch (offset = 2Ch) [reset = 1h]
Figure 2-242. Register 2Ch
7 6 5 4 3 2 1 0
ROOT_CLK_TX1_DIV_M
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-246. Register 2C Field Descriptions
Bit Field Type Reset Description
4-0
ROOT_CLK_TX1_
DIV_M
R/W 1h
For lanes[0:1]/[4:5], M-value in Divide ratio of M/N for
generating the root-clock for DAC_JESD from 48x clock. All
the other internal clocks like DUC_WR_CLK and
JESD_RX_CLK are derieved from this root clock