Texas Instruments AFE79 Series - 2.4.67 Register 62 h (offset = 62 h) [reset = 2 h]; 2.4.68 Register 63 h (offset = 63 h) [reset = 3 h]; 2.4.69 Register 64 h (offset = 64 h) [reset = Fh]; 2.4.70 Register 65 h (offset = 65 h) [reset = 4 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.4.67 Register 62h (offset = 62h) [reset = 2h]
Figure 2-296. Register 62h
7 6 5 4 3 2 1 0
LID2
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-300. Register 62 Field Descriptions
Bit Field Type Reset Description
4-0 LID2 R/W 2h JESD Lane ID for lane2/6
2.4.68 Register 63h (offset = 63h) [reset = 3h]
Figure 2-297. Register 63h
7 6 5 4 3 2 1 0
LID3
R/W-3h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-301. Register 63 Field Descriptions
Bit Field Type Reset Description
4-0 LID3 R/W 3h JESD Lane ID for lane3/7
2.4.69 Register 64h (offset = 64h) [reset = Fh]
Figure 2-298. Register 64h
7 6 5 4 3 2 1 0
JESD_CLEAR_DATA LANE_ENA
R/W-0h R/W-Fh
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-302. Register 64 Field Descriptions
Bit Field Type Reset Description
7-4
JESD_CLEAR_DA
TA
R/W 0h When asserted, zeros the JESD block output data
3-0 LANE_ENA R/W Fh
JESD lane enable
[0] - lane0/4 enable
[1] - lane1/5 enable
[2] - lane2/6 enable
[3] - lane3/7 enable
2.4.70 Register 65h (offset = 65h) [reset = 4h]
Figure 2-299. Register 65h
7 6 5 4 3 2 1 0
K_COUNTER_THRESH
R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset