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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-2143. Register 55D Field Descriptions
Bit Field Type Reset Description
1-0
FB_AGC_BAND0_
LNA_PHASE16[9:8
]
R/W 0h
LNA Phase for Band0 for temp index 16 in case of External
LNA Control , Phase for DVGA Index 16 in case of External
DVGA control
2.14.247 Register 55Eh (offset = 55Eh) [reset = 0h]
Figure 2-2130. Register 55Eh
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE17[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2144. Register 55E Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BAND0_
LNA_PHASE17[7:0
]
R/W 0h
LNA Phase for Band0 for temp index 17 in case of External
LNA Control , Phase for DVGA Index 17 in case of External
DVGA control
2.14.248 Register 55Fh (offset = 55Fh) [reset = 0h]
Figure 2-2131. Register 55Fh
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE1
7[9:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2145. Register 55F Field Descriptions
Bit Field Type Reset Description
1-0
FB_AGC_BAND0_
LNA_PHASE17[9:8
]
R/W 0h
LNA Phase for Band0 for temp index 17 in case of External
LNA Control , Phase for DVGA Index 17 in case of External
DVGA control
2.14.249 Register 560h (offset = 560h) [reset = 0h]
Figure 2-2132. Register 560h
7 6 5 4 3 2 1 0
FB_AGC_BAND0_LNA_PHASE18[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-2146. Register 560 Field Descriptions
Bit Field Type Reset Description
7-0
FB_AGC_BAND0_
LNA_PHASE18[7:0
]
R/W 0h
LNA Phase for Band0 for temp index 18 in case of External
LNA Control , Phase for DVGA Index 18 in case of External
DVGA control