Texas Instruments AFE79 Series - 2.5.37 Register 4 Bh (offset = 4 Bh) [reset = 0 h]; 2.5.38 Register 4 Ch (offset = 4 Ch) [reset = 1 h]; 2.5.39 Register 4 Dh (offset = 4 Dh) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.37 Register 4Bh (offset = 4Bh) [reset = 0h]
Figure 2-533. Register 4Bh
7 6 5 4 3 2 1 0
0 0 0 DDC_RD_CLK_FB_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-538. Register 4B Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
DDC_RD_CLK_FB
_DIV_N_M1
R/W 0h
N-1 value of ddc divider.
Output of this divider, clock frequency should match the
FBAB/FBCD interface rate
2.5.38 Register 4Ch (offset = 4Ch) [reset = 1h]
Figure 2-534. Register 4Ch
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_RX1_DIV_M
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-539. Register 4C Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
JESD_CLK_RX1_
DIV_M
R/W 1h
M value of jesd divider.
Output of this divider, clock frequency should match STX1/5
rate i.e. lane _rate/40 or lane_rate/33
2.5.39 Register 4Dh (offset = 4Dh) [reset = 0h]
Figure 2-535. Register 4Dh
7 6 5 4 3 2 1 0
0 0 0 JESD_CLK_RX1_DIV_N_M1
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-540. Register 4D Field Descriptions
Bit Field Type Reset Description
7-5 0 R/W 0h Must read or write 0
4-0
JESD_CLK_RX1_
DIV_N_M1
R/W 0h
N-1 value of jesd divider.
Output of this divider, clock frequency should match STX1/5
rate i.e. lane _rate/40 or lane_rate/33