Texas Instruments AFE79 Series User Manual

PLL Register Map www.ti.com
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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-29. Register 41 Field Descriptions
Bit Field Type Reset Description
7-4 reserved R/W 0h
3-3 reserved R/W 0h
2-1 CTL_CP_BIAS R/W 0h
Scaling factor for Charge pump current.
0 -> 1x
1 -> 0.5x
2 -> 2x
3 -> 1.5x
0-0 reserved R/W 0h
2.2.5 Register 43h (offset = 43h) [reset = 18h]
Figure 2-28. Register 43h
7 6 5 4 3 2 1 0
CTL_LPF_R reserved reserved reserved
R/W-0h R/W-1h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-30. Register 43 Field Descriptions
Bit Field Type Reset Description
7-5 CTL_LPF_R R/W 0h
lpf res is given by
R = 638+638/4*CTL_LPF_R<2:0>
4-4 reserved R/W 1h
3-3 reserved R/W 1h
2-0 reserved R/W 0h
2.2.6 Register 5Ch (offset = 5Ch) [reset = 0h]
Figure 2-29. Register 5Ch
7 6 5 4 3 2 1 0
reserved SYSREF_LATCH_DELAY
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-31. Register 5C Field Descriptions
Bit Field Type Reset Description
7-3 reserved R/W 0h
2-0
SYSREF_LATCH_
DELAY
R/W 0h
CLK delay for sysref latching
0 : 0p
1 : 20p
2 : T/2+20p
3 : 40p
4 : T/2+40p
5 : 60p
6 : T/2+60p
7 : 80p
Where T is the time period of the clock

Texas Instruments AFE79 Series Specifications

General

Brand	Texas Instruments
Model	AFE79 Series
Category	Control Unit
Language	English