Texas Instruments AFE79 Series - 2.5.59 Register 67 h (offset = 67 h) [reset = 0 h]; 2.5.60 Register 68 h (offset = 68 h) [reset = 0 h]; 2.5.61 Register 69 h (offset = 69 h) [reset = 88 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.59 Register 67h (offset = 67h) [reset = 0h]
Figure 2-555. Register 67h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 CFG_FB_LFSR
_LOAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-560. Register 67 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
CFG_FB_LFSR_L
OAD
R/W 0h
when set to 1, CFG_FB_LFSR_SEED_VAL is used as seed
for all fb M/N dividers
2.5.60 Register 68h (offset = 68h) [reset = 0h]
Figure 2-556. Register 68h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 SERDES_INPU
T_ORDER_FLI
P_DISABLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-561. Register 68 Field Descriptions
Bit Field Type Reset Description
7-1 0 R/W 0h Must read or write 0
0-0
SERDES_INPUT_
ORDER_FLIP_DIS
ABLE
R/W 0h
By default the JESD IP gives data to transmit MSB first. But
serdes sends LSB first, so requires a data flip at the input.
When 1, no order flip is done.
2.5.61 Register 69h (offset = 69h) [reset = 88h]
Figure 2-557. Register 69h
7 6 5 4 3 2 1 0
SERDES_FIFO_READ_DLY_LANE1 SERDES_FIFO_READ_DLY_LANE0
R/W-8h R/W-8h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-562. Register 69 Field Descriptions
Bit Field Type Reset Description
7-4
SERDES_FIFO_R
EAD_DLY_LANE1
R/W 8h
Controls STX2/6
Fifo offset (JESD_TX to SERDES handoff)
3-0
SERDES_FIFO_R
EAD_DLY_LANE0
R/W 8h
Controls STX1/5
Fifo offset (JESD_TX to SERDES handoff)