Texas Instruments AFE79 Series - 2.5.112 Register A7 h (offset = A7 h) [reset = 1 h]; 2.5.113 Register A8 h (offset = A8 h) [reset = 1 h]; 2.5.114 Register A9 h (offset = A9 h) [reset = 0 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-612. Register A6 Field Descriptions
Bit Field Type Reset Description
7-7 0 R/W 0h Must read or write 0
6-6 LINK2_ADJDIR R/W 0h JESD link config for STX 3,4/7,8
5-5 LINK2_PHADJ R/W 0h JESD link config for STX 3,4/7,8
4-0 0 R/W 0h Must read or write 0
2.5.112 Register A7h (offset = A7h) [reset = 1h]
Figure 2-608. Register A7h
7 6 5 4 3 2 1 0
LINK2_SCR 0 0 LINK2_ILA_L_M1
R/W-0h R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-613. Register A7 Field Descriptions
Bit Field Type Reset Description
7-7 LINK2_SCR R/W 0h
JESD link config for STX 3,4/7,8
For JESD-B/C
When 1, scrambler (present between transport layer and link
layer) is enabled
1+x^14+x^15
0 : scrambler disabled
1 : scrambler enabled
6-5 0 R/W 0h Must read or write 0
4-0 LINK2_ILA_L_M1 R/W 1h
JESD link config for STX 3,4/7,8
Used only when link2_jesd_ila_config_override is 1.
Else L derived from LMFS is used.
2.5.113 Register A8h (offset = A8h) [reset = 1h]
Figure 2-609. Register A8h
7 6 5 4 3 2 1 0
LINK2_ILA_F_M1
R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-614. Register A8 Field Descriptions
Bit Field Type Reset Description
7-0 LINK2_ILA_F_M1 R/W 1h
JESD link config for STX 3,4/7,8
Used only when link2_jesd_ila_config_override is 1.
Else F derived from LMFS is used.
2.5.114 Register A9h (offset = A9h) [reset = 0h]
Figure 2-610. Register A9h
7 6 5 4 3 2 1 0
LINK2_ILA_K_M1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset