Texas Instruments AFE79 Series - 2.3.38 Register 4 Ch (offset = 4 Ch) [reset = 10 h]; 2.3.39 Register 4 Dh (offset = 4 Dh) [reset = 32 h]

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Serial Interface Register Maps
Table 2-81. Register 4B Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH7_
SEL
R/W 7h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX8.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2-0
TXOCTETPATH6_
SEL
R/W 6h
Selects the input SERDES-Tx lane for data that is normally
supposed to be on STX7.
0 : sel lane0 data
1 : sel lane1 data
2 : sel lane2 data
3 : sel lane3 data
4 : sel lane4 data
5 : sel lane5 data
6 : sel lane6 data
7 : sel lane7 data
2.3.38 Register 4Ch (offset = 4Ch) [reset = 10h]
Figure 2-79. Register 4Ch
7 6 5 4 3 2 1 0
TXOCTETPATH1_CLK_SEL TXOCTETPATH0_CLK_SEL
R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-82. Register 4C Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH1_
CLK_SEL
R/W 1h
Selects the input SERDES-Tx lane for clk data that is normally
supposed to be on STX2.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
TXOCTETPATH0_
CLK_SEL
R/W 0h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX1.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2.3.39 Register 4Dh (offset = 4Dh) [reset = 32h]
Figure 2-80. Register 4Dh
7 6 5 4 3 2 1 0
TXOCTETPATH3_CLK_SEL TXOCTETPATH2_CLK_SEL
R/W-3h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset