Texas Instruments AFE79 Series - 2.5.45 Register 55 h (offset = 55 h) [reset = 15 h]; 2.5.46 Register 56 h (offset = 56 h) [reset = 15 h]

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SBAU337–May 2020
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Serial Interface Register Maps
2.5.45 Register 55h (offset = 55h) [reset = 15h]
Figure 2-541. Register 55h
7 6 5 4 3 2 1 0
0 0 CTRL_FB_ROOT_CLK_P3 CTRL_FB_ROOT_CLK_P1 CTRL_FB_ROOT_CLK_P0
R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-546. Register 55 Field Descriptions
Bit Field Type Reset Description
7-6 0 R/W 0h Must read or write 0
5-4
CTRL_FB_ROOT_
CLK_P3
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
3-2
CTRL_FB_ROOT_
CLK_P1
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
1-0
CTRL_FB_ROOT_
CLK_P0
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
2.5.46 Register 56h (offset = 56h) [reset = 15h]
Figure 2-542. Register 56h
7 6 5 4 3 2 1 0
0 0 CTRL_DDC_RD_CLK_FB CTRL_DDC_RD_CLK_RX2 CTRL_DDC_RD_CLK_RX1
R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-547. Register 56 Field Descriptions
Bit Field Type Reset Description
7-6 0 R/W 0h Must read or write 0
5-4
CTRL_DDC_RD_C
LK_FB
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled
3-2
CTRL_DDC_RD_C
LK_RX2
R/W 1h
Used for M/N clock divider disabling, for lower power
When MSB = 0, M/N divider is enabled/disabled based on
functionality
When MSB = 1, M/N divider is enabled/disabled using spi
register i.e. LSB bit.
LSB = 0, M/N divider disabled
LSB = 1, M/N divider enabled