DAC JESD Register Map
www.ti.com
318
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-381. Register BC Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT2[7:0]
R/W 0h short test pattern input
2.4.149 Register BDh (offset = BDh) [reset = 0h]
Figure 2-378. Register BDh
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT2[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-382. Register BD Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT2[15:8]
R/W 0h short test pattern input
2.4.150 Register BEh (offset = BEh) [reset = 0h]
Figure 2-379. Register BEh
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT3[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-383. Register BE Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT3[7:0]
R/W 0h short test pattern input
2.4.151 Register BFh (offset = BFh) [reset = 0h]
Figure 2-380. Register BFh
7 6 5 4 3 2 1 0
JESD_SHORTTEST_INPUT3[15:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-384. Register BF Field Descriptions
Bit Field Type Reset Description
7-0
JESD_SHORTTES
T_INPUT3[15:8]
R/W 0h short test pattern input